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Operation
A zero value for DTL causes a delay-after-transfer value of 8192/CLKIN frequency.
Standard delay after transfer = 17/CLKIN frequency (DT = 0)
Adequate delay between transfers must be specified for long data streams because the QSPI
module requires time to load a transmit RAM entry for transfer. Receiving devices need at
least the standard delay between successive transfers. If CLKIN is operating at a slower
rate, the delay between transfers must be increased proportionately.
14.4.4 Transfer Length
There are two transfer length options. The user can choose a default value of 8 bits or a
programmed value of 8 to 16 bits inclusive. The programmed value must be written into
QMR[BITS]. The bits per transfer enable (BITSE) field in the command RAM determines
whether the default value (BITSE = 0) or the BITS[3–0] value (BITSE = 1) is used.
QMR[BITS] gives the required number of bits to be transferred, with 0b0000 representing
16.
14.4.5 Data Transfer
Operation is initiated by setting QDLYR[SPE]. Shortly after QDLYR[SPE] is set, the QSPI
executes the command at the command RAM address pointed to by QWR[NEWQP]. Data
at the pointer address in transmit RAM is loaded into the data serializer and transmitted.
Data that is simultaneously received is stored at the pointer address in receive RAM.
When the proper number of bits has been transferred, the QSPI stores the working queue
pointer value in QWR[CPTQP], increments the working queue pointer, and loads the next
data for transfer from the transmit RAM. The command pointed to by the incremented
working queue pointer is executed next unless a new value has been written to
QWR[NEWQP]. If a new queue pointer value is written while a transfer is in progress, then
that transfer is completed normally.
When the CONT bit in the command RAM is set, the QSPI_CS signals are asserted
between transfers. When CONT is cleared, QSPI_CS[0:3] are negated between transfers.
The QSPI_CS signals are not high impedance.
When the QSPI reaches the end of the queue, it asserts the SPIF flag, QIR[SPIF]. If
QIR[SPIFE] is set, an interrupt request is generated when QIR[SPIF] is asserted. Then the
QSPI clears QDLYR[SPE] and stops, unless wraparound mode is enabled.
Wraparound mode is enabled by setting QWR[WREN]. The queue can wrap to pointer
address 0x0, or to the address specified by QWR[NEWQP], depending on the state of
QWR[WRTO].
In wraparound mode, the QSPI cycles through the queue continuously, even while
requesting interrupt service. QDLYR[SPE] is not cleared when the last command in the
queue is executed. New receive data overwrites previously received data in the receive
14-8
MCF5272 User's Manual
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