Motorola DigitalDNA ColdFire MCF5272 User Manual page 20

Paragraph
Number
19.17 Operating Mode Configuration Pins............................................................... 19-36
19.18 Power Supply Pins .......................................................................................... 19-37
20.1 Features ............................................................................................................. 20-1
20.2 Bus And Control Signals .................................................................................. 20-1
20.2.1 Address Bus (A[22:0]).................................................................................. 20-2
20.2.2 Data Bus (D[31:0]) ....................................................................................... 20-2
20.2.3 Read/Write (R/W)......................................................................................... 20-2
20.2.4 Transfer Acknowledge (TA)......................................................................... 20-3
20.2.5 Transfer Error Acknowledge (TEA)............................................................. 20-4
20.3 Bus Exception: Double Bus Fault..................................................................... 20-4
20.4 Bus Characteristics............................................................................................ 20-5
20.5 Data Transfer Mechanism................................................................................. 20-5
20.5.1 Bus Sizing ..................................................................................................... 20-6
20.6 External Bus Interface Types.......................................................................... 20-10
20.6.1 Interface for FLASH/SRAM Devices with Byte Strobes........................... 20-10
20.6.2 Interface for FLASH/SRAM Devices without Byte Strobes...................... 20-15
20.7 Burst Data Transfers ....................................................................................... 20-20
20.8 Misaligned Operands ...................................................................................... 20-20
20.9 Interrupt Cycles............................................................................................... 20-21
20.10 Bus Errors ....................................................................................................... 20-22
20.11 Bus Arbitration................................................................................................ 20-24
20.12 Reset Operation............................................................................................... 20-24
20.12.1 Master Reset ............................................................................................... 20-25
20.12.2 Normal Reset .............................................................................................. 20-26
20.12.3 Software Watchdog Timer Reset Operation............................................... 20-27
20.12.4 Soft Reset Operation................................................................................... 20-28
21.1 Overview........................................................................................................... 21-1
21.2 JTAG Test Access Port and BDM Debug Port................................................. 21-2
21.3 TAP Controller.................................................................................................. 21-3
21.4 Boundary Scan Register.................................................................................... 21-4
21.5 Instruction Register........................................................................................... 21-7
21.6 Restrictions ....................................................................................................... 21-8
21.7 Non-IEEE 1149.1 Operation............................................................................. 21-9
xx
CONTENTS
Title
Chapter 20
Bus Operation
Chapter 21
IEEE 1149.1 Test Access Port (JTAG)
MCF5272 User's Manual
Page
Number