Motorola DigitalDNA ColdFire MCF5272 User Manual page 522

Debug AC Timing Specifications
Table 23-23. IEEE 1149.1 (JTAG) AC Timing Specifications (Continued)
J11 TCK falling edge to boundary scan data valid (signal from driven or three-state)
J12 TCK falling edge to boundary scan data high impedance
Figure 23-23 shows JTAG timings listed in Table 23-23.
TDI, TMS
Boundary
Scan Data
Inputs
TRST
Boundary
Scan Data
Outputs
23.4.9 QSPI Electrical Specifications
Table 23-24 lists QSPI timings.
Table 23-24. QSPI Modules AC Timing Specifications
Name
2
QS1 SDLCK high to QSPI chip selects valid.
2
QS2 SDLCK high to QSPI chip selects invalid. (Output hold)
2
QS3 SDLCK high to QSPI_CLK valid.
2
QS4 SDLCK high to QSPI_CLK invalid. (Output hold)
3
QS5 QSPI_CLK high to QSPI_DOUT valid.
3
QS6 QSPI_CLK high to QSPI_DOUT invalid. (Output hold)
QS7 SDCLK high to QSPI_DOUT valid.
2
QS8 SDCLK high to QSPI_DOUT invalid. (Output hold)
3
QS9 QSPI_DIN to QSPI_CLK high. (Input setup)
23-28
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
J1
TCK
J2a
J4
J6
J9
TDO
J11
Figure 23-23. IEEE 1149.1 (JTAG) Timing
Characteristic
MCF5272 User's Manual
J3a
V
h
V
l
J2b
J5
J7
J8
J10
J12
1
— 35 nS
— 35 nS
J3b
0–66 MHz
Unit
Min Max
— 25 nS
2 — nS
— 12.5 nS
2 — nS
— 18 nS
2 — nS
— 30 nS
5 — nS
5 — nS