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Chapter 9
SDRAM Controller
This chapter describes configuration and operation of the synchronous DRAM controller
component of the SIM including a general description of signals involved in SDRAM
operations. It provides interface information for memory configurations using most
common SDRAM devices for both 16- and 32-bit wide data buses. The chapter concludes
with signal timing diagrams.
9.1 Overview
The MCF5272 incorporates an SDRAM controller, whose main features are as follows:
• Glueless interface to a variety of JEDEC-compliant SDRAM devices.
• MCF5272 data bus width of 16 or 32 bits to SDRAM memory array
• 16- to 256-Mbit device support
• Dedicated bank address pins to provide pin out compatibility for different SDRAM
sizes with a single printed circuit board layout
• Page size from 256–1024 column address locations
• 6-1-1-1 timing for burst-read; 3-1-1-1 timing for burst-write accesses (assuming a
page hit at 66 MHz)
• CAS latencies of 1 and 2
• Up to four concurrently activated banks
• SDRAM power down and self refresh
• Refresh timer prescaler supports system clock down to 5 MHz maintaining a
15.6-µS refresh cycle
• Auto initialization of SDRAM
9.2 SDRAM Controller Signals
The SDRAM controller provides all required signals for glueless interfacing to a variety of
JEDEC-compliant SDRAM devices. RAS/CAS address multiplexing and the SDRAM pin
A10 auto-precharge function is software configurable for different page sizes. To maintain
refresh capability without conflicting with concurrent accesses on the address and data
buses, RAS0, CAS0, SDWE, SDBA[0:1], SDCLKE, A10_PRECHG, and the SDRAM
Chapter 9. SDRAM Controller
9-1
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