Motorola DigitalDNA ColdFire MCF5272 User Manual page 432

Bus Control Signals
peripheral accesses, these outputs indicate that data is to be latched or driven onto a byte of
the data when driven low. BSn signals are asserted only to the memory bytes used during a
read or write access.
BSn signals are asserted during accesses to on-chip peripherals but not to on-chip SRAM,
cache, or ROM. During SDRAM accesses, these signals indicate a byte transfer between
SDRAM and the MCF5272 when driven high.
For SRAM or FLASH devices, BS[3:0] outputs should be connected to individual byte
strobe signals.
For SDRAM devices, BS[3:0] should be connected to individual SDRAM DQM signals.
Note that most SDRAMs associate DQM3 with the MSB, in which case BS3 should be
connected to the SDRAM's DQM3 input.
Table 19-3. Byte Strobe Operation for 32-Bit Data Bus
Table 19-4. Byte Strobe Operation for 16-Bit Data Bus
In 16-bit bus mode, longword accesses are performed as two
sequential word accesses.
Table 19-5 shows how BS[3:0] should be connected to DQMx for 16- and 32-bit SDRAM
configurations.
19-18
BS3 BS2 BS1 BS0 Access Type Data Located On
1 1 1 1
1 1 1 0
1 1 0 1
1 0 1 1
0 1 1 1
1 1 0 0
0 0 1 1
0 0 0 0
BS1 BS0 Access Type Data Located On
1 1 None
1 0 Byte
0 1 Byte
0 0 Word
NOTE
MCF5272 User's Manual
None —
Byte D[7:0]
D[15:8]
D[23:16]
D[31:24]
Word D[15:0]
D[31:16]
Longword D[31:0]
—
D[7:0]
D[15:8]
D[15:0]