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Real-Time Trace Support
the other allows operand data to be displayed (debug data, DDATA). The processor status
may not be related to the current bus transfer.
External development systems can use PST outputs with an external image of the program
to completely track the dynamic execution path. This tracking is complicated by any
change in flow, especially when branch target address calculation is based on the contents
of a program-visible register (variant addressing). DDATA outputs can be configured to
display the target address of such instructions in sequential nibble increments across
multiple processor clock cycles, as described in Section 5.3.1, "Begin Execution of Taken
Branch (PST = 0x5)." Two 32-bit storage elements form a FIFO buffer connecting the
processor's high-speed local bus to the external development system through PST[3:0] and
DDATA[3:0]. The buffer captures branch target addresses and certain data values for
eventual display on the DDATA port, one nibble at a time starting with the least significant
bit (lsb).
Execution speed is affected only when both storage elements contain valid data to be
dumped to the DDATA port. The core stalls until one FIFO entry is available.
Table 5-2 shows the encoding of these signals.
Chapter 5. Debug Support
5-3
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