Motorola DigitalDNA ColdFire MCF5272 User Manual page 529

Table A-9. DMA Module Memory Map (Continued)
MBAR
[31:24]
Offset
0x00E8
0x00EC
0x00F0
MBAR
[31:24]
Offset
0x0100 UART0 Mode Register
1/2 (U0MR1/U0MR2)
0x0104 UART0 Status (U0SR)
0x0104 UART0 Clock Select
Register (U0CSR)
0x0108 UART0 Command
Register (U0CR)
0x010C UART0 Receive Buffer
(U0RxB)
0x010C UART0 Transmit Buffer
(U0TxB)
0x0110 UART0 CTS Change
Register (U0CCR)
0x0110 UART0 Auxiliary Control
Register (U0ACR)
0x0114 UART0 Interrupt Status
Register (U0ISR)
0x0114 UART0 Interrupt Mask
Register (U0IMR)
0x0118 UART0 Baud Prescaler
MSB (U0BG1)
0x011C UART0 Baud Prescaler
LSB (U0BG2)
0x0120 UART0 AutoBaud MSB
Register (U0ABR1)
0x0124 UART0 AutoBaud LSB
Register (U0ABR2)
0x0128 UART0 TxFIFO
Control/Status Register
(U0TxFCSR)
0x012C UART0 RxFIFO
Control/Status Register
(U0RxFCSR)
0x0134 UART0 CTS Unlatched
Input (U0IP)
[23:16]
DMA Byte Count Register (DBCR)
DMA Source Address Register (DSAR)
DMA Destination Address Register (DDAR)
Table A-10. UART0 Module Memory Map
[23:16]
Appendix A. List of Memory Maps
List of Memory Map Tables
[15:8]
[15:8]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[7:0]
[7:0]
A-5