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MCF5272
Interface 0
Interface 1
Two of Motorola's MC145574 S/T transceivers are shown connected to ports 0 and 1. The
frame sync control signal FSC0 is connected to S/T transceiver one, while FSC1 is
connected to transceiver two.
Figure 13-42 shows an example of the IDL bus timing relationship of the S/T transceivers
when in standard IDL2 8-bit mode with a common frame sync.
DCL
FSC0
FSC1
Din0/
B1
Dout0
Din1/
B1
Dout1
DGNT0
DREQ0
Din0
Dout0
FSC0
DCL0
DGNT1
DREQ1
Din1
Dout1
FSC1
DCL1
Figure 13-41. Two-Line Remote Access
MC145574 #1
B2
D
B2
D
MC145574 #2
Figure 13-42. Standard IDL2 8-Bit mode
Chapter 13. Physical Layer Interface Controller (PLIC)
Application Examples
MC145574 #1
DGrant
DRequest
Tx
Rx
IDL SYNC
IDL CLK
MC145574 #2
DGrant
DRequest
Tx
Rx
IDL SYNC
IDL CLK
13-43
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