Motorola DigitalDNA ColdFire MCF5272 User Manual page 182

Interrupt Controller Registers
If the core initiates an interrupt acknowledge cycle prior to the PIVR being programmed,
the interrupt controller returns the uninitialized interrupt vector (0x0F). If the core initiates
an interrupt acknowledge cycle after the PIVR has been initialized, but there is no interrupt
pending, the interrupt controller returns the user a spurious interrupt vector (0xxxx0_0000).
Because the interrupt controller responds to all interrupt acknowledges, a bus error situation
cannot occur during an interrupt-acknowledge cycle.
7
Field
Reset
R/W
Address
Figure 7-9. Programmable Interrupt Vector Register (PIVR)
Table 7-7 describes PIVR fields.
Bits Field
7-5 IV These bits provide the high three bits of the interrupt vector for interrupt acknowledge cycles from all
sources. To conform to the core interrupt vector allocation, these bits should be set equal to or greater
than 010. See Table 2-3.
4-0 — Reserved, should be cleared.
Table 7-8 lists the values for the five least significant bits of the interrupt vector. The vector
numbers shown assume PIVR[IV]=0b010. If another value of PIVR[IV] is used, the vector
numbers would change accordingly.
Vector Number
64
65
66
67
68
69
70
71
72
73
74
75
7-10
5
IV
Table 7-7. PIVR Field Descriptions
Table 7-8. MCF5272 Interrupt Vector Table
Bits 4–0 Source
00000 Reserved
00001 INT1
00010 INT2
00011 INT3
00100 INT4
00101 TMR1
00110 TMR2
00111 TMR3
01000 TMR4
01001 UART1
01010 UART2
01011 PLIP
MCF5272 User's Manual
4
—
0000_1111
R/W
MBAR + 0x03F
Description
User Spurious Interrupt
External Interrupt Input 1
External Interrupt Input 2
External Interrupt Input 3
External Interrupt Input 4
PLIC 2KHz Periodic
0
Function
Timer 1
Timer 2
Timer 3
Timer 4
UART 1
UART 2