Table of Contents
Advertisement
Reset Operation
During the software watchdog timer reset period, all outputs are driven to their default
levels. Once RSTO negates, all bus signals continue to remain in this state until the
ColdFire core begins the first bus cycle for reset exception processing.
During a software watchdog timer reset, SCE[RSTSRC] is set to 0b10 to indicate the
software watchdog as the source of the previous reset.
The levels of the mode pins are not sampled during a software
watchdog reset. If the port size and acknowledge features of
CS0 are different from the values programmed in CSBR0 and
CSOR0 at the time of the software watchdog reset, you must
assert RSTI during software watchdog reset to cause the mode
pins to be resampled.
20.12.4 Soft Reset Operation
If the soft reset bit, SCR[SOFTRST], is programmed to generate a reset, RSTO is asserted
for 128 clocks, resetting all external devices as with a normal or master reset. All internal
peripherals with the exception of the SIM, chip select, interrupt controller, GPIO module,
and SDRAM controller are reset also. The SDRAM controller is reset only when
DRESETEN is tied low.
SCR[SOFTRST] is automatically cleared at the end of the 128 clock period. Software can
monitor this bit to determine the end of the soft reset. Figure 20-24 shows the timing of
RSTO when asserted by SCR[SOFTRST].
CLKIN
SoftRST
RSTO
INTERNAL
PERIPHERALS
RSTI
20-28
NOTE:
T = 128
CLK CYCLES
Figure 20-24. Soft Reset Timing
MCF5272 User's Manual
Advertisement
Table of Contents
