Motorola DigitalDNA ColdFire MCF5272 User Manual page 192

SDRAM Controller Signals
bank selects are dedicated SDRAM signals.
Figure 9-1 shows the SDRAM controller signal configuration.
Internal 32-Bit Address Bus
Table 9-1 describes SDRAM controller signals.
Table 9-1. SDRAM Controller Signal Descriptions
Signal
A10_PRECHG A10 precharge strobe. A precharge cycle occurs only after a page miss. During precharge, the
SDRAM writes the designated on-chip RAM page buffer back into the SDRAM array.
Precharge latency is set in SDTR[RP]. The reset value is 2 cycles, RP = 01.
BS[3:0] For SDRAM devices, these outputs should be connected to individual DQM signals. During
SDRAM accesses, these signals indicate a byte transfer between SDRAM and the MCF5272
when asserted. Note that most SDRAMs associate DQM3 with the MSB, in which case BS3
should be connected to the SDRAM's DQM3 input, and so forth.
CAS0 SDRAM column address strobe output
DRESETEN DRESETEN is asserted to indicate that the SDRAM controller is to be reset whenever RSTI
asserts. If DRESETEN is negated, RSTI does not affect the SDRAM controller, which
continues to refresh external memory. This is useful for debug situations where a reset of the
device is required without losing data located in SDRAM. DRESETEN is normally tied high or
low depending on system requirements. It should never be tied to RSTI or RSTO.
RAS0 SDRAM row address strobe output
SDA[13:0]/ Fourteen address signals are multiplexed to form SDRAM_ADR[13:0], which are used for
A[22:0] connecting to SDRAM devices as large as 256 Mbits. SDRAM can be configured for 16- or
32-bit wide interface to the MCF5272 data bus. For an SDRAM array with a 32-bit data bus,
SDRAM address signals are multiplexed starting with A2. For a 16-bit data bus, address
signals are multiplexed starting with A1.
9-2
SDRAM Controller
Address Multiplexer
Dynamic Bus Sizer
Figure 9-1. SDRAM Controller Signals
MCF5272 User's Manual
1 SDRAMCS/CS7
1 RAS0
1
CAS0
1 SDWE
4 BS[3:0]
2 SDBA[1:0]
1 SDCLKE
1 SDCLK
1 A10_PRECHG
8 A[22:15]
10 A[11:2]/SDA[9:0]
2 A[14:13/SDA[12:11]
32 D[31:0]
Description