Motorola DigitalDNA ColdFire MCF5272 User Manual page 19

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19.14 Queued Serial Peripheral Interface (QSPI) Signals ........................................ 19-28
19.14.1 QSPI Synchronous Serial Data Output (QSPI_Dout)................................. 19-28
19.14.2 QSPI Synchronous Serial Data Input (QSPI_Din) ..................................... 19-28
19.14.3 QSPI Serial Clock (QSPI_CLK/BUSW1).................................................. 19-28
19.14.4 Synchronous Peripheral Chip Select 0 (QSPI_CS0/BUSW0).................... 19-28
19.14.5 Synchronous Peripheral Chip Select 1 (QSPI_CS1/PA11) ........................ 19-28
19.14.6 Synchronous Peripheral Chip Select 2 (QSPI_CS2/URT1_CTS) .............. 19-29
19.14.7 Synchronous Peripheral Chip Select 3 (PA7/DOUT3/QSPI_CS3)............ 19-29
19.15 Physical Layer Interface Controller TDM Ports............................................. 19-29
19.15.1 GCI/IDL TDM Port 0. ................................................................................ 19-29
19.15.1.1 Frame Sync (FSR0/FSC0/PA8).............................................................. 19-29
19.15.1.2 D-Channel Grant (DGNT0/PA9)............................................................ 19-29
19.15.1.3 Data Clock (DCL0/URT1_CLK) ........................................................... 19-30
19.15.1.4 Serial Data Input (DIN0/URT1_RxD).................................................... 19-30
19.15.1.5 UART1 CTS (URT1_CTS/QSPI_CS2) ................................................. 19-30
19.15.1.6 UART1 RTS (URT1_RTS/INT5)........................................................... 19-30
19.15.1.7 Serial Data Output (DOUT0/URT1_TxD) ............................................. 19-30
19.15.1.8 D-Channel Request(DREQ0/PA10) ....................................................... 19-31
19.15.1.9 QSPI Chip Select 1 (QSPI_CS1/PA11).................................................. 19-31
19.15.2 GCI/IDL TDM Port 1 ................................................................................. 19-31
19.15.2.1 GCI/IDL Data Clock (DCL1/GDCL1_OUT)......................................... 19-31
19.15.2.2 GCI/IDL Data Out (DOUT1) ................................................................. 19-31
19.15.2.3 GCI/IDL Data In (DIN1) ........................................................................ 19-31
19.15.2.4 GCI/IDL Frame Sync (FSC1/FSR1/DFSC1) ......................................... 19-32
19.15.2.5 D-Channel Request (DREQ1/PA14) ...................................................... 19-32
19.15.2.6 D-Channel Grant (DGNT1_INT6/PA15_INT6) .................................... 19-32
19.15.3 GCI/IDL TDM Ports 2 and 3...................................................................... 19-32
19.15.3.1 GCI/IDL Delayed Frame Sync 2 (DFSC2/PA12) .................................. 19-33
19.15.3.2 GCI/IDL Delayed Frame Sync 3 (DFSC3/PA13) .................................. 19-33
19.15.3.3 QSPI_CS3, Port 3 GCI/IDL Data Out 3, PA7
19.15.3.4 INT4 and Port 3 GCI/IDL Data In (INT4/DIN3) ................................... 19-33
19.16 JTAG Test Access Port and BDM Debug Port............................................... 19-34
19.16.1 Test Clock (TCK/PSTCLK) ....................................................................... 19-34
19.16.2 Test Mode Select and Force Breakpoint (TMS/BKPT).............................. 19-34
19.16.3 Test and Debug Data Out (TDO/DSO)....................................................... 19-34
19.16.4 Test and Debug Data In (TDI/DSI) ............................................................ 19-35
19.16.5 JTAG TRST and BDM Data Clock (TRST/DSCLK) ................................ 19-35
19.16.6 Motorola Test Mode Select (MTMOD)...................................................... 19-35
19.16.7 Debug Transfer Error Acknowledge (TEA) ............................................... 19-35
19.16.8 Processor Status Outputs (PST[3:0]) .......................................................... 19-35
19.16.9 Debug Data (DDATA[3:0])........................................................................ 19-36
19.16.10 Device Test Enable (TEST)........................................................................ 19-36
CONTENTS
(PA7/DOUT3/QSPI_CS3) .................................................................. 19-33
Contents
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