Motorola DigitalDNA ColdFire MCF5272 User Manual page 516

Debug AC Timing Specifications
Table 23-18 lists timing for IDL slave mode.
Table 23-18. IDL Slave Mode Timing, PLIC Ports 0–3
Name
1
P14 FSR0, FSR1 period
P15a FSR0 or FSC0 valid before the falling edge of DCL0 (setup time)
P22 DCL clock frequency
P23 DCL pulse width high
P24 DCL pulse width low
P15b FSR1 or FSC1 valid before the falling edge of DCL1 (setup time)
P16a DCL0 to FSR0 or FSC0 input Invalid (hold time)
P16b DCL1 to FSR1 or FSC1 input Invalid (hold time)
P17a Delay from rising edge of DCL0 to low-z and valid data on DOUT0
P17b Delay from rising edge of DCL1 to low-z and valid data on DOUT1 and
DOUT3
P19a Delay from rising edge of DCL0 to high-z on DOUT0
P19b Delay from rising edge of DCL1 to high-z on DOUT1 and DOUT3
2
P20 Delay from rising edge of DCL1 to DFSC2, DFSC3 Invalid (output hold)
P25 Data valid on DIN0 before falling edge of DCL0 (setup time)
P25 Data valid on DIN1, DIN3 before falling edge of DCL1 (setup time)
P26 Data valid on DIN0 after falling edge of DCL0 (hold time)
P26 Data valid on DIN1, DIN3 after falling edge of DCL1 (hold time)
1
FSR occurs on average every 125 µs.
2
In IDL slave mode, DCL may be any frequency multiPe of 8 KHz between 256 KHz and 4.096 MHz inclusive.
Figure 23-18 shows IDL slave timings listed in Table 23-18.
23-22
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Characteristic
MCF5272 User's Manual
Min Typ Max Unit
— 125 — µs
25 — — nS
256 — 4096 Khz
45 — 55 % of DCL period
45 — 55 % of DCL period
25 — — nS
25 — — nS
25 — — nS
— — 30 nS
— — 30 nS
— — 30 nS
— — 30 nS
2 — — nS
25 — — nS
25 — — nS
25 — — nS
25 — — nS