Table 19-2. Signal Name and Description by Pin Number
Map
BGA
0 (Reset)
Pin
A1
DDATA3
A2
DDATA1
A3
TEA
A4
TDI
A5
D16
A6
D18
A7
D21
A8
D22
A9
BS0
A10
RAS0
A11
A13
A12
A2
A13
A3
A14
A4
B1
PST0
B2
DDATA2
B3
MTMOD
B4
TMS
B5
A20
B6
D17
B7
D20
B8
D23
B9
SDWE
B10
SDCS/
CS7
B11
A12
B12
A1
B13
A5
Pin Functions
1
2
–
–
–
–
–
–
DSI
–
D0
–
D2
–
D5
–
D6
–
–
–
–
–
SDA12
SDA11
SDA1
SDA0
SDA2
SDA1
SDA3
SDA2
–
–
–
–
–
–
BKPT
–
–
–
D1
–
D4
–
D7
–
–
–
–
–
SDA11
–
SDA0
–
SDA4
SDA3
Chapter 19. Signal Descriptions
Name
3
–
DDATA3
–
DDATA1
–
TEA
–
TDI/DSI
–
D16/D0
–
D18/D2
–
D21/D5
–
D22/D6
–
BS0
–
RAS0
–
A13/SDA12/SDA11
–
A2/SDA1/SDA0
–
A3/SDA2/SDA1
–
A4/SDA3/SDA2
–
PST0
–
DDATA2
–
MTMOD
–
TMS/BKPT
–
A20
–
D17/D1
–
D20/D4
–
D23/D7
–
SDWE
–
SDCS / CS7
–
A12/SDA11
–
A1/SDA0
–
A5/SDA4/SDA3
Signal List
Description
Debug data 3
Debug data 1
BDM debug transfer
error acknowledge
JTAG test data in/BDM
data in
D16/D0
D18/D2
D21/D5
D22/D6
Byte strobe 0
SDRAM row select
strobe
A13/SDRAM-16bit
A12/SDRAM-32bit A11
A2/SDRAM-16bit
A1/SDRAM-32bit A0
A3/SDRAM-16bit
A2/SDRAM-32bit A1
A4/SDRAM-16bit
A3/SDRAM-32bit A2
Internal processor
status 0
Debug data 2
0 selects JTAG mode, 1
selects BDM mode
JTAG test mode/BDM
select breakpoint input
A20
D17/D1
D20/D4
D23/D7
SDRAM write enable
SDRAM chip
select/CS7
A12/SDRAM-16bit A11
A1/SDRAM-16bit A0
A5/SDRAM-16bit
A4/SDRAM-32bit A3
19-9
I/O
O
O
I
I
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
O
I/O
I/O
I/O
O
O
O
O
O