Transmitter And Receiver Operating Modes - Motorola DigitalDNA ColdFire MCF5272 User Manual

16.5.2 Transmitter and Receiver Operating Modes

Figure 16-24 is a functional block diagram of the transmitter and receiver showing the
command and operating registers, which are described generally in the following sections
and described in detail in Section 16.3, "Register Descriptions."
UART Transmit
FIFO (URB)
(24 Bytes)
UART Transmit
FIFO (URB)
(24 Bytes)
Figure 16-24. Transmitter and Receiver Functional Diagram
16.5.2.1 Transmitting
The transmitter is enabled through the UART command register (UCRn). When it is ready
to accept a character, the UART sets USRn[TxRDY]. The transmitter converts parallel data
from the CPU to a serial bit stream on TxD. It automatically sends a start bit followed by
the programmed number of data bits, an optional parity bit, and the programmed number
of stop bits. The lsb is sent first. Data is shifted from the transmitter output on the falling
edge of the clock source.
After the stop bits are sent, if no new character is in the transmitter holding register, the TxD
output remains high (mark condition) and the transmitter empty bit, USRn[TxEMP], is set.
Transmission resumes and TxEMP is cleared when the CPU loads a new character into the
UART transmitter buffer (UTBn). If the transmitter receives a disable command, it
continues until any character in the transmitter shift register is completely sent.
If the transmitter is reset through a software command, operation stops immediately (see
Section 16.3.5, "UART Command Registers (UCRn)"). The transmitter is reenabled
through the UCRn to resume operation after a disable or software reset.
UART
UART Command Register (UCR0)
UART Mode Register 1 (UMR1)
UART Mode Register 2 (UMR2)
UART Status Register (USR0)
Transmitter FIFO
Transmitter Shift Register
Receiver FIFO
Receiver Shift Register
Chapter 16. UART Modules
W
R/W
R/W
R
W
R
Operation
External
Interface
TXD
RXD
16-23