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13.2.3.5 GCI/IDL D-Channel Contention
Typically, when the CPU wants to transmit a D-channel packet, it starts the HDLC framer.
In IDL mode, when the CPU can start sending data from the prepared HDLC frame to the
D-channel transmit register, it asserts DREQ by setting the appropriate DRQ bit in the
PDRQR register. The D-channel controller hardware looks for a valid DGRANT back from
the layer 1 transceiver and, assuming DREQ is also valid, begins transmitting the
D-channel packet. PDCSR[DGn] reflects the value of the dedicated DGRANT pin. Refer
to the MC145574 data sheet for SCIT mode information.
In GCI mode the only D-channel contention control is provided by PLCRn[G/S],
Section 13.5.7, "Port Configuration Registers (P0CR–P3CR)." Provided the PLIC operates
in SCIT mode, PDCSR[DGn], Section 13.5.19, "D-Channel Status Register (PDCSR)," is
defined by the state of PLCRn[G/S], and is used to control D-channel transmission along
with PDRQR[DRQn], Section 13.5.20, "D-Channel Request Register (PDRQR)." In GCI
mode, the PLIC ports do not support any other form of D-channel contention such as the
indirect mode found on the Motorola MC145574. In GCI mode, the DGRANT pin function
found in IDL mode is disabled and the pin can be defined for other functions. Please note
that the D-channel periodic interrupts in both the receive and transmit direction are not
disabled even though the shift register is disabled by DREQ, DGRANT, and
PDRQR[DCNTIn]
configuration.
An override mechanism for D-channel contention control is provided through the
D-channel ignore DCNTI bit.
Figure 13-8 illustrates this functionality:
13.2.4 GCI/IDL Looping Modes
The PLIC ports can be configured to operate in various looping modes as shown in
Figure 13-9. These modes are useful for local and remote system diagnostic functions.
The loopback modes are independent signal loopbacks for the respective ports. These
loopbacks allow for the echoing of local or remote information. In auto-echo or
remote-loopback modes there is no time switching or time slot assignment function. All
data received on Din is transmitted on Dout during the same time slot. Similarly, in
(Section 13.5.20,
Shift Register Enable
Figure 13-8. D-Channel Contention
Chapter 13. Physical Layer Interface Controller (PLIC)
"D-Channel
Request
GCI/IDL Block
Register
(PDRQR)")
DGRANT
DREQ
DCNTI
13-9
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