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8.2.1 Chip Select Base Registers (CSBR0–CSBR7)
The CSBRs, Figure 8-1, provide a model internal bus cycle against which to match actual
bus cycles to determine whether a specific chip select should assert. A bus cycle in a specific
chip select register causes the assertion of the corresponding external chip select.
31
Field
BA
Reset
CSBR0: 0x0000_0x01
CSBR4: 0x0000_4300; CSBR5: 0x0000_5300; CSBR6: 0x0000_6300; CSBR7: 0x0000_7700
R/W
Addr
Figure 8-1. Chip Select Base Registers (CSBRn)
Table 8-2 describes CSBRn fields.
Bits
Name
31–12
BA
Base address. The starting address of the memory space covered by the chip select. BA is
compared with bits 31–12 of the access to determine whether the current bus cycle is intended
for this chip select. Any combination of BA bits can be masked in the associated CSOR.
11–10
EBI
External bus interface modes. These modes are used to multiplex outputs and determine timing
of the appropriate bus interface module onto the device pins.
00 16-/32-bit SRAM/ROM. For 16-/32-bit wide memory devices with byte strobe inputs.
CSBR0[EBI] = 00 at reset. Affects all chip selects.
01 SDRAM. One physical bank of SDRAM consisting of 16–256 Mbit devices. CSOR7[WS] must
be set to 0x1F. Affects only CS7/SDCS.
10 Reserved
11 Use SRAM/ROM timing for 8-bit devices without byte strobe inputs.
9–8
BW
Bus width. Determines data bus size of the memory-mapped resource for all chip selects except
CS0. It is assumed that boot code for the processor is accessed through the global chip select
CS0, so the initial bus width for this chip select must be configured at reset. QSPI_CS0/BUSW0
and QSPI_CLK/BUSW1 are used to program the bus width for CS0 at reset.
00 Longword (32 bits)
01 Byte (8 bits)
10 Word (16 bits)
11 Cache line (32 bits)
7
SUPER
Supervisor mode.
0 Bus cycle may be in user or supervisor mode (neglecting conditions imposed by setting CTM).
1 The chip select asserts a match only if the transfer modifier indicates a supervisor mode
access. A user access matching BA causes an access error.
SUPER, CTM, TT, and TM are used to restrict bus access. For example, if TT and TM indicate a
user data access and SUPER and CTM are both set, no accesses can occur.
6–5
TT
Transfer type. TT and TM may be used to further qualify the address match. If CTM is set, TT and
TM must match the access types for the chip select to assert. See the description of TM.
12 11
10
9
EBI
BW
1
; CSBR1: 0x0000_1300; CSBR2: 0x0000_2300; CSBR3: 0x0000_3300;
0x040 (CSBR0); 0x048 (CSBR1); 0x050 (CSBR2); 0x058 (CSBR3);
0x060 (CSBR4); 0x068 (CSBR5); 0x070 (CSBR6); 0x078 (CSBR7)
Table 8-2. CSBRn Field Descriptions
Chapter 8. Chip Select Module
8
7
6
5
SUPER
TT
R/W
Description
Chip Select Registers
4
2
1
TM
CTM ENABLE
0
8-3
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