Interrupt Cycles - Motorola DigitalDNA ColdFire MCF5272 User Manual

longword is misaligned at an address that is not evenly divisible by four. However, because
operands can reside at any byte boundary, they can be misaligned.
Although the MCF5272 does not enforce any alignment restrictions for data operands
(including program counter (PC) relative data addressing), significant performance
degradation can occur when additional bus cycles are required for longword or word
operands that are misaligned. For maximum performance, data items should be aligned on
their natural boundaries. All instruction words and extension words must reside on word
boundaries. An address error exception occurs with any attempt to prefetch an instruction
word at an odd address.
The MCF5272 converts misaligned operand accesses to a sequence of aligned accesses.
Figure 20-18 illustrates the transfer of a longword operand from a byte address to a 32-bit
port, requiring more than one bus cycle. Figure 20-19 is similar to the example illustrated
in Figure 20-18 except that the operand is word-sized and the transfer requires only two bus
cycles.
31
Transfer 1
Transfer 2
Transfer 3
Figure 20-18. Example of a Misaligned Longword Transfer
31
Transfer 1
Transfer 2
Figure 20-19. Example of a Misaligned Word Transfer

20.9 Interrupt Cycles

All interrupt vectors are internally generated. The MCF5272 does not support external
interrupt acknowledge cycles. The System Integration Module prioritizes all interrupt
requests and issues the appropriate vector number in response to an interrupt acknowledge
cycle. Refer to the System Integration chapter for details on the interrupt vectors and their
priorities.
When an external peripheral device requires the services of the CPU, it can signal the
ColdFire core to take an interrupt exception. The external peripheral devices use the
interrupt request signals (INTx) to signal an interrupt condition to the MCF5272. The
interrupt exception transfers control to a routine that responds appropriately.
There are a total of six external interrupt inputs, INT[6:1]. Depending on the pin
configuration between three and six of these pins are available. Each interrupt input pin is
24 23
—
Byte 0
— —
—
Byte 3
24 23
— —
—
Byte 1
Chapter 20. Bus Operation
16 15 8 7
—
Byte 1
—
16 15 8 7
—
—
Interrupt Cycles
A[2:0]
0
—
001
Byte 2 010
—
100
A[2:0]
0
Byte 0 001
—
100
20-21