Table of Contents
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Paragraph
Number
1.1
MCF5272 Key Features...................................................................................... 1-1
1.2
MCF5272 Architecture ....................................................................................... 1-4
1.2.1
Version 2 ColdFire Core................................................................................. 1-4
1.2.2
System Integration Module (SIM).................................................................. 1-5
1.2.2.1
External Bus Interface ................................................................................ 1-5
1.2.2.2
Chip Select and Wait State Generation ...................................................... 1-5
1.2.2.3
System Configuration and Protection ......................................................... 1-5
1.2.2.4
Power Management .................................................................................... 1-6
1.2.2.5
Parallel Input/Output Ports ......................................................................... 1-6
1.2.2.6
Interrupt Inputs ........................................................................................... 1-6
1.2.3
UART Module ................................................................................................ 1-6
1.2.4
Timer Module ................................................................................................. 1-7
1.2.5
Test Access Port.............................................................................................. 1-7
1.3
System Design ................................................................................................... 1-7
1.3.1
System Bus Configuration .............................................................................. 1-7
1.4
MCF5272-Specific Features ............................................................................... 1-8
1.4.1
Physical Layer Interface Controller (PLIC).................................................... 1-8
1.4.2
Pulse-Width Modulation (PWM) Unit ........................................................... 1-8
1.4.3
Queued Serial Peripheral Interface (QSPI)..................................................... 1-8
1.4.4
Universal Serial Bus (USB) Module .............................................................. 1-9
2.1
Features and Enhancements.............................................................................. 2-11
2.1.1
Decoupled Pipelines ...................................................................................... 2-11
2.1.1.1
Instruction Fetch Pipeline (IFP)................................................................ 2-12
2.1.1.2
Operand Execution Pipeline (OEP) .......................................................... 2-13
2.1.1.2.1
2.1.1.2.2
CONTENTS
About This Book
Chapter 1
Chapter 2
Illegal Opcode Handling....................................................................... 2-13
Hardware Multiply/Accumulate (MAC) Unit ...................................... 2-13
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