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Port Control Registers
17.2 Port Control Registers
The port control registers are used to configure all pins that carry signals multiplexed from
different on-chip modules. Each pin is configured with a two-bit field. Pin functions are
referred to as function 0b00–0b11. The function 0 signals corresponding to GPIO ports A
and B are immediately available after reset.
Wherever a signal function includes a GPIO port bit, the function defaults to an input after
a reset and can be read in the corresponding port data register.
Pin functions are generally grouped logically. For example, all UART1 signals are
multiplexed with port B and have the control register function code of 0b01.
There is no port C control register. Port C is enabled when the 16-bit-wide external data bus
mode is selected at reset by the input level on QSPI_DOUT/WSEL. The port D control
register is used to configure pins that have multiple functions (0b01 through 0b11) but no
GPIO function.
Do not attempt to program a pin function that is not defined.
Where no function is defined, the function code is labeled
'Reserved' and is considered invalid. Programming any control
register field with a reserved value has an unpredictable effect
on the corresponding pin's operation.
Reserved function codes cannot be reliably read. Attempts to
read them yield undetermined values.
MBAR
[31:24]
Offset
0x0080
0x0084
Port A Data Direction Register (PADDR)
0x0086
0x0088
0x008C
Port B Data Direction Register (PBDDR)
0x008E
0x0094
Port C Data Direction Register (PCDDR)
0x0096
0x0098
17.2.1 Port A Control Register (PACNT)
PACNT is used to configure pins that source signals multiplexed with GPIO port A.
17-2
CAUTION:
Table 17-2. GPIO Port Register Memory Map
[23:16]
Port A Control Register (PACNT)
Port B Control Register (PBCNT)
Reserved
Reserved
Port D Control Register (PDCNT)
MCF5272 User's Manual
[15:8]
Reserved
Port A Data Register (PADAT)
Reserved
Port B Data Register (PBDAT)
Reserved
Port C Data Register (PCDAT)
[7:0]
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