Motorola DigitalDNA ColdFire MCF5272 User Manual page 213

Internal Clock
T0
SDCLK
Precharge
SDCR[SLEEP]
SDCLKE
SDADR[13:0]
A10_PRECHG
SDBA[1:0]
SDCS
RAS0
CAS0
SDWE
Figure 9-15 shows the timing for exiting SDRAM self-refresh mode. Note that
SDCR[GSL] is sampled on the rising edge of the internal clock. If it is 0, as it is here,
SDRAM controller signals become active on the following negative clock edge.
T1 T2 T3 T4
Self
All Banks NOP
Refresh
Figure 9-14. Enter SDRAM Self-Refresh Mode
Chapter 9. SDRAM Controller
T5 T6 T7 T8
SDRAM Interface
T9 T10 T11 T12 T13
9-23