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4. Execute the STOP instruction. This must be the next instruction executed after the
write to the ALPR.
Sleep mode is exited by an interrupt request from by either an external device or an on-chip
peripheral as detailed in Table 6-7.
The sequence to enter stop mode is:
1. Set PMR[MOS]; clear PMR[SLPEN].
2. Set the CPU interrupt priority level in the status register (SR). Interrupts below this
level do not reactivate the CPU.
3. Perform a write access with any data to ALPR.
4. Execute the STOP instruction. This must be the next instruction executed after the
write to the ALPR.
Stop mode is exited by an interrupt request from an external device as detailed in Table 6-7.
Interrupt Source
Interrupts, INT6–INT2
Interrupt, INT1
USART1, USART2
QSPI
USB
PLIC
General purpose I/O
General purpose timers
Ethernet
DMA controller
PWM
Hardware watchdog timer No
Software watchdog timer
6.2.7 Device Identification Register (DIR)
The DIR, Figure 6-7, contains a value representing the identification mark for the
MCF5272 device. This register contains the same value as the JTAG IDCODE register. The
version number field will change if a new revision of the MCF5272 is created.
Table 6-7. Exiting Sleep and Stop Modes
Exit Sleep
Yes
Yes
Yes, interrupt and Rx signal change
Yes
Yes, interrupt and Rx signal change
Yes, interrupt
No
Yes, interrupt
Yes, interrupt
Yes, interrupt
No
Yes, interrupt
Chapter 6. System Integration Module (SIM)
Programming Model
Exit Stop USB Wake-on-Ring
Yes
No
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
6-11
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