Table of Contents
Advertisement
PLIC Timing Generator
FSC0
FSC1
P1CR[SFSM]
Port 0
GCI/IDL
Port 1
GCI/IDL
Port 2
GCI/IDL
Port 3
GCI/IDL
Figure 13-11. PLIC Internal Timing Signal Routing
DCL0/URT1_CLK
PA8/FSC0/FSR0
O192K
CKI[1:0]
13.3.3 Frame Sync Synthesis
Figure 13-11 illustrates the relationships between the various frame sync clocks. DFSC1 is
generated through programmable delay 1 referenced to DFSC0. DFSC2 and DFSC3 are
generated through programmable delays 2 and 3 referenced to DFSC1. Note well the
following:
13-14
P0SDR[15:0]
DFSC0
Prog Delay 0
P1SDR[15:0]
DCL0
DFSC0
DCL1
FSC1
P2SDR[15:0]
DCL1
DFSC2
P3SDR[15:0]
DCL1
DFSC3
Multiply
Mux
Block
CMULT[2:0]
Figure 13-12. PLIC Clock Generator
MCF5272 User's Manual
2-KHz to CPU
SFSC Gen
P0CR[M2-M0]
Mux 0
DFSC1
Prog Delay 1
Pin
Mux 1
P1CR[M/S]
Prog Delay 2
Prog Delay 3
Divider
Block
FDIV[2:0]
Pin
DCL0/URT1_CLK
PA8/FSC0/FSR0
DCL1/GDCL1_OUT
FSC1/FSR1/DFSC1
DFSC2
DFSC3
GDCL
Gen_FSC
Advertisement
Table of Contents
