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List of Memory Map Tables
Table A-1. On-Chip Module Base Address Offsets from MBAR
Ethernet Module Registers
USB Module Registers
CPU
SPACE
NAME
ADDRESS
0x0002
(CACR)
0x0004
(ACR0)
0x0005
(ACR1)
0x008x
A7:A0
0x008x
D7:D0
0x0801
(VBR)
0x080E
CCR
0x080F
PC
0x0C00
ROMBAR
0x0C04
RAMBAR
0x0C0F
MBAR
MBAR must only be written using the MOVEC instruction.
Writing to address MBAR+0x0000 causes unpredictable
device operation.
Table A-3. On-Chip Peripherals and Configuration Registers Memory Map
MBAR
[31:24]
Offset
0x0000
0x0004
System Configuration Register (SCR)
0x0006
0x0008
0x000E
0x0010
A-2
Module
Table A-2. CPU Space Registers Memory Map
SYSTEM CONFIGURATION
Size
REGISTERS
32
Cache Control Register
32
Cache Access Control Register 0
32
Cache Access Control Register 1
32
Address registers A7:A0
32
Data registers D7:D0
32
Vector Base Register
8
Condition Code Register (Debug only)
32
Program Counter (Debug only)
32
ROM Base Address Register
32
SRAM Base Address Register
32
Module Base Address Register
[23:16]
Module Base Address Register, Read Only (MBAR)
Reserved
Power Management Register (PMR)
Reserved
Device Identification Register (DIR)
MCF5272 User's Manual
Module Base
Address
MBAR+0x0800
ENET_Base
MBAR+0x1000
USB_Base
Program Access
MOVEC
MOVEC
MOVEC
MOVE
MOVE
MOVEC
MOVE to/from CCR
MOVEC
MOVEC
MOVEC
NOTE:
[15:8]
System Protection Register (SPR)
Activate Low Power Register (ALPR)
Mnemonic
Debug Access
RCREG, WCREG
RCREG, WCREG
RCREG, WCREG
RAREG, WAREG
RDREG, WDREG
RCREG, WCREG
RCREG, WCREG
RCREG, WCREG
RCREG, WCREG
RCREG, WCREG
[7:0]
Reserved
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