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PLIC Registers
Field
Reset
R/W
Addr
Figure 13-30. GCI C/I Channel Transmit Status Register (PGCITSR)
Bits
Name
7–4
—
3
ACK3
2
ACK2
1
ACK1
0
ACK0
13.5.19 D-Channel Status Register (PDCSR)
All bits in this register are read only and are cleared on hardware or software reset. The
register is also cleared after a read operation.
The PDCSR register contains the D-channel status bits for all four ports on the MCF5272.
Field
Reset
R/W
Addr
Figure 13-31. D-Channel Status Register (PDCSR)
Bits
Name
7–6
—
Reserved, should be cleared.
5
DG1
D-channel grant, port 1.
0 Default reset value.
1 In IDL mode, indicates the status of DGRANT. When the external DGNT has a logic 1,
13-32
7
—
Table 13-13. PGCITSR Field Descriptions
Reserved, should be cleared.
Acknowledge, port 3.
0 Default reset value.
1 Set by the C/I channel controller to indicate that the previous C/I data has
been transmitted in two successive C/I words. The ACK bit is automatically
cleared by the CPU when the PGCITSR register has been read.
Acknowledge, port 2. See ACK3.
Acknowledge, port 1. See ACK3.
Acknowledge, port 0. See ACK3.
7
6
5
—
DG1
Table 13-14. PDCSR Field Descriptions
the corresponding DG1/DG0 bit is set. In GCI mode, DG1 and DG0 reflects the
inverted value of the SCIT bit. The significance of this bit is the same in IDL or GCI
mode, that is, in IDL mode when the DG bit is set, the D channel is granted. In GCI
mode when the DG bit is set, this corresponds to the GO condition. In both cases the D
channel is granted and communication may commence.
MCF5272 User's Manual
4
3
2
ACK3
ACK2
0000_0000
Read Only
MBAR + 0x37F
Description
4
3
2
DG0
DC3
DC2
0000_0000
Read Only
MBAR + 0x383
Description
1
0
ACK1
ACK0
1
0
DC1
DC0
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