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QSPI_CLK
QSPI_Dout
15
msb
QSPI_Din
15
A
QSPI_CS
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
Figure 14-4. QSPI Clocking and Data Transfer Example
14.5.2 QSPI Delay Register (QDLYR)
Figure 14-5 shows the QSPI delay register.
15
14
Field
SPE
Reset
R/W
Address
Table 14-4 gives QDLYR field descriptions.
Bits
Name
15
SPE
QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in
the command RAM. Automatically cleared by the QSPI when a transfer completes.The user can
also clear this bit to abort transfer unless QIR[ABRTL] is set. The recommended method for
aborting transfers is to set QWR[HALT].
14–8
QCD
QSPILCK Delay. When the DSCK bit in the command RAM, is set this field determines the length
of the delay from assertion of the chip selects to valid QSPI_CLK transition.
7–0
DTL
Delay after transfer.When the DT bit in the command RAM sets this field determines the length of
delay after the serial transfer.
14
13
12
11
10
14
13
12
11
10
QCD
0000_0100_0000_0100
Figure 14-5. QSPI Delay Register (QDLYR)
Table 14-4. QDLYR Field Descriptions
Chapter 14. Queued Serial Peripheral Interface (QSPI) Module
9
8
7
6
5
9
8
7
6
5
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
8
7
R/W
MBAR + 0x00A4
Description
Programming Model
4
3
2
1
0
4
3
2
1
0
DTL
B
0
14-11
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