Table 20-4. Data Bus Requirement for Read Cycles
Transfer Size A[1:0]
Byte
Word
Longword
Line
Table 20-5 lists the transfer size, A[1:0], and the corresponding pattern of the data transfer
for write cycles from the internal multiplexer of the MCF5272 to the external data bus. For
example, if a longword transfer is generated to a 16-bit port, the MCF5272 starts the cycle
with A[1:0] set to 0x0 and reads the first word. The address in then incremented to 0x2 and
the second word is read. The data for both word reads is taken from D[31:16]. Bytes labeled
"X" are don't cares.I
Table 20-5. Internal to External Data Bus Multiplexer–Write Cycle
32-Bit Port
D[31:24] D[23:16] D[15:8]
00
Byte 0
X
01
X
Byte 1
10
X
X
11
X
X
00
Byte 0
Byte 1
01
—
—
10
X
X
11
—
—
00
Byte 0
Byte 1
01
—
—
10
—
—
11
—
—
00
Byte 0
Byte 1
01
—
—
10
—
—
11
—
—
Transfer Size A[1:0]
D[31:24] D[23:16] D[15:8] D[7:0]
Byte
00
01
10
11
Word
00
01
10
11
Chapter 20. Bus Operation
External Data Bytes Required
16-Bit Port
D[7:0]
D[31:24] D[23:16]
X
X
Byte 0
X
X
X
Byte 2
X
Byte 2
X
Byte 3
X
X
X
Byte 0
—
—
—
Byte2
Byte 3
Byte 2
—
—
—
Byte 2
Byte 3
Byte 0
—
—
—
—
—
Byte 2
—
—
—
Byte 2
Byte 3
Byte 0
—
—
—
—
—
Byte 2
—
—
—
External Data Bus Connection
OP3
X
X
OP3
OP3
X
OP3
X
OP3
OP3
OP3
X
OP2
OP3
X
OP3
X
X
OP2
OP3
OP2
OP3
X
X
Data Transfer Mechanism
8-Bit Port
D[31:24]
X
Byte 0
Byte 1
Byte 1
X
Byte 2
Byte 3
Byte 3
Byte 1
Byte 0
—
Byte 1
Byte 3
Byte 2
—
Byte 3
Byte 1
Byte 0
—
Byte 1
Byte 3
Byte 2
—
Byte 3
Byte 1
Byte 0
—
Byte 1
Byte 3
Byte 2
—
Byte 3
X
X
X
OP3
X
X
OP3
X
20-9