Gci/Idl Delayed Frame Sync 2 (Dfsc2/Pa12) - Motorola DigitalDNA ColdFire MCF5272 User Manual

Physical Layer Interface Controller TDM Ports

19.15.3.1 GCI/IDL Delayed Frame Sync 2 (DFSC2/PA12)

IDL/GCI Modes: DFSC2 is used as a programmable delayed frame sync for external
IDL/GCI devices that use port 2 but are connected to the port 1 data pins. Port 2 uses the
DFSC2 frame sync internally to ensure alignment with external devices synchronized with
DFSC2. The width of this signal can be configured for 1, 2, 8, or 16 DCL clocks duration.
The location of this frame sync is programmable in single clock increments up to a
maximum count of 0x3FF.
Port A mode: I/O pin PA12.
19.15.3.2 GCI/IDL Delayed Frame Sync 3 (DFSC3/PA13)
Output pin DFSC3. This active high signal is used as a programmable delayed frame sync
for external IDL/GCI devices that use port 3 but are connected to the port 1 or port 3 data
pins. Port 3 uses the DFSC3 frame sync internally to ensure alignment with external devices
synchronized with DFSC3. The width of this signal can be configured for 1, 2, 8, or 16 DCL
clocks duration. The location of this frame sync is programmable in single clock increments
up to a maximum count of 0x3FF.
Port A mode: I/O pin PA13.
19.15.3.3 QSPI_CS3, Port 3 GCI/IDL Data Out 3, PA7
(PA7/DOUT3/QSPI_CS3)
QSPI mode: The QSPI chip select, QSPI_CS3, is the default configuration after device
reset.
IDL mode: This pin can be configured as a dedicated output for clocking data out of IDL
port 3. Data is clocked out of DOUT3 on the rising edge of DCL1. After device reset port
3 is connected to DOUT1 by setting a bit in the PLIC module configuration register, this
pin can be configured as a dedicated output for IDL/GCI port 3.
GCI mode: This pin can be configured as a dedicated output for clocking data out of GCI
port 3. Data is clocked out of DOUT3 on the rising edge of DCL1. DCL1 is twice the bit
rate, that is, two clocks per data bit. This is done by setting a bit in the PLIC module
configuration register this pin can be configured as a dedicated output for IDL/GCI port 3.
Port A mode: I/O pin PA7.
19.15.3.4 INT4 and Port 3 GCI/IDL Data In (INT4/DIN3)
IDL mode: This pin can be configured as a dedicated input, DIN3, for clocking data into
IDL port 3. Data is clocked into DIN3 on the falling edge of DCL1. Data is clocked into
DIN3 on the falling edge of DCL1. This is done by setting a bit in the PLIC module
configuration register. Note that the appropriate bits must be set in the pin configuration
register to reassign this pin from the interrupt module to the PLIC module.
Chapter 19. Signal Descriptions 19-33