Motorola DigitalDNA ColdFire MCF5272 User Manual page 238

Programming Model
Table 11-13. describes the MII_DATA fields.
Bits Name
31–30 ST Start of frame delimiter. Must be programmed to 01 for a valid MII management frame
29–28 OP Operation code. This field must be programmed to 10 (read) or 01(write) to generate a valid
MII management frame. A value of 11 produces a read frame operation while a value of 00
produces a write frame operation, but these frames are not MII-compliant.
27–23 PA PHY address. Specifies one of up to 32 attached PHY devices
22–18 RA Register address. Specifies one of up to 32 registers within the specified PHY device
17–16 TA Turn around. Must be programmed to 10 to generate a valid MII management frame.
15–0 DATA Management frame data. Field for data to be written to or read from PHY register
To perform a read or write operation on the MII management interface, the MII_DATA
register is written by the user. To generate a valid read or write management frame, the ST
field must be written with a 01 pattern, the OP field must be written with a 01 (management
register write frame) or 10 (management register read frame), and the TA field must be
written with a 10. If other patterns are written to these fields, a frame is generated but will
not comply with the IEEE 802.3 MII definition. OP field = 1x produces a read-frame
operation, while OP = 0x produces a write-frame operation.
To generate an 802.3-compliant MII management interface write frame (write to a PHY
register), the user must write {01 01 PHYAD REGAD 10 DATA} to the MII_DATA
register. Writing this pattern causes the control logic to shift out the data in the MII_DATA
register following a preamble generated by the control state machine. The contents of
MII_DATA are altered as the contents are serially shifted, and are unpredictable if read by
the user. Once the write management frame operation completes, the MII interrupt is
generated. At this time, the contents of the MII_DATA register match the original value
written.
To generate an MII management interface read frame (read a PHY register), the user must
write {01 10 PHYAD REGAD 10 XXXX} to MII_DATA (the contents of the DATA field
are a don't care). Writing this pattern causes the control logic to shift out the data in the
MII_DATA register following a preamble generated by the control state machine.The
contents of the MII_DATA register are altered as the contents are serially shifted, and are
unpredictable if read by the user. Once the read management frame operation completes,
the MII interrupt is generated. At this time the contents of the MII_DATA register matches
the original value written except for the DATA field, whose contents are replaced by the
value read from the PHY register.
If the MII_DATA register is written while frame generation is in progress, the frame
contents are altered. Software should use the MII interrupt to avoid writing to the
MII_DATA register while frame generation is in progress.
11-18
Table 11-13. MII_DATA Field Descriptions
MCF5272 User's Manual
Description