Motorola DigitalDNA ColdFire MCF5272 User Manual page 118

Programming Model
development system using the debug serial interface or by the operating system running on
the processor core. Software is responsible for guaranteeing that accesses to these resources
are serialized and logically consistent. Hardware provides a locking mechanism in the CSR
to allow the external development system to disable any attempted writes by the processor
to the breakpoint registers (setting CSR[IPW]). BDM commands must not be issued if the
MCF5272 is using the WDEBUG instruction to access debug module registers or the
resulting behavior is undefined.
These registers, shown in Figure 5-4, are treated as 32-bit quantities, regardless of the
number of implemented bits.
31
31
31
31
31
31
Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don't care).
All debug control registers are writable from the external development system or the CPU via the
WDEBUG instruction.
CSR is write-only from the programming model. It can be read or written through the BDM port using the
and
RDMREG WDMREG
These registers are accessed through the BDM port by new BDM commands,
, described in Section 5.5.3.3, "Command Set Descriptions." These commands
RDMREG
contain a 5-bit field, DRc, that specifies the register, as shown in Table 5-3.
DRc[4–0]
0x00 Configuration/status register
0x01–0x05 Reserved
0x06 Address attribute trigger register
0x07 Trigger definition register
0x08 Program counter breakpoint register
5-6
15 7
15
15
15
15
15
.
commands
Figure 5-4. Debug Programming Model
Table 5-3. BDM/Breakpoint Registers
Register Name
MCF5272 User's Manual
0
AATR Address attribute trigger register
0
ABLR Address low breakpoint register
ABHR Address high breakpoint register
0
CSR Configuration/status register
0
DBR Data breakpoint register
DBMR Data breakpoint mask register
0
PBR PC breakpoint register
PBMR PC breakpoint mask register
0
TDR Trigger definition register
Abbreviation
CSR
—
AATR
TDR
PBR
WDMREG
Initial State Page
0x0000_0000 p. 5-9
— —
0x0000_0005 p. 5-7
0x0000_0000 p. 5-13
— p. 5-12
and