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19.12.10 Receive Error (E_RxER/PB14)
Ethernet mode: E_RxER is an input signal which when asserted along with E_RxDV
signals that the PHY has detected an error in the current frame. When E_RxDV is not
asserted E_RxER has no effect. Applies to MII mode operation.
Port B mode: This pin can also be configured as PB14 I/O.
19.12.11 Management Data Clock (E_MDC/PB15)
Ethernet mode: E_MDC is an output clock which provides a timing reference to the PHY
for data transfers on the E_MDIO signal. Applies to MII mode operation.
Port B mode: This pin can also be configured as I/O pin PB15.
19.12.12 Management Data (E_MDIO)
The bidirectional E_MDIO signal transfers control information between the external PHY
and the media-access controller. Data is synchronous to E_MDC. Applies to MII mode
operation. This signal is an input after reset. When the FEC is operated in 10Mbps 7-wire
interface mode, this signal should be connected to Vss.
19.12.13 Transmit Error (E_TxER)
Ethernet mode: When the E_TxER output is asserted for one or more clock cycles while
E_TxEN is also asserted, the PHY sends one or more illegal symbols. E_TxER has no
effect at 10 Mbps or when E_TxEN is negated. Applies to MII mode operation.
19.12.14 Carrier Receive Sense (E_CRS)
E_CRS is an input signal which when asserted signals that transmit or receive medium is
not idle. Applies to MII mode operation.
19.13 PWM Module Signals
(PWM_OUT0–PWM_OUT2])
PWM_OUT0–PWM_OUT2 are the outputs of the compare logic within the pulse-width
modulator (PWM) modules.
• PWM_OUT0 is always available.
• PWM_OUT1 is multiplexed with TOUT1.
• PWM_OUT2 is multiplexed with TIN1.
PWM Module Signals (PWM_OUT0–PWM_OUT2])
Chapter 19. Signal Descriptions
19-27
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