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The CPU should service the B1 and B2 registers once every 500 µS. Overrun conditions
can be avoided only if the CPU services these registers in a timely manner.
The MCF5272 has 4 GCI/IDL interfaces. Thus the theoretical maximum is twelve 32-bit
data registers to be read. For most applications the typical number is less.
Figure 13-3 shows the shift register, shadow register, internal bus register, and multiplexor
for each B receive channel.
After reset, the B- and D-channel shift registers and shadow registers are initialized to all
ones.
D
IN
64 Kbps
START
Shadow Register
B1, B2, Receive
Data Register
Figure 13-3. GCI/IDL B-Channel Receive Data Register Demultiplexing
13.2.2 GCI/IDL B- and D-Channel Transmit Data Registers
DCL
B1 Shift Register
Dout
B1
The maximum transmission rate for each GCI/IDL port is 144 Kbps: the sum of two
64-Kbps B channels and one 16-Kbps D-channel. Frames of B
packed together in a similar way to the receive side.
Shift Register (B1 or B2)
8 bits
8 bits
B2 Shift Register
B2
32
Internal Bus
Figure 13-4. GCI/IDL Transmit Data Flow
Chapter 13. Physical Layer Interface Controller (PLIC)
8 bits
DEMUX
8-KHz Rate
8 bits
8 bits
2-KHz transfer and interrupt
32
32 bits
32
D Shift Register
D
32
GCI/IDL Block
END
Internal Bus
Multiplexing
Circuitry
8
, B
, and D-channels are
1
2
13-5
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