Debug Ac Timing Specifications - Motorola DigitalDNA ColdFire MCF5272 User Manual

Debug AC Timing Specifications
23.4 Debug AC Timing Specifications
Table 23-9 lists specifications for the debug AC timing parameters shown in Figure 23-8.
Num
D1
D2
D3
1
D4
D5
1
DSCLK and DSI are synchronized internally. D4 is measured from the
synchronized DSCLK input relative to the rising edge of PSTCLK.
Figure 23-7 shows real-time trace timing for the values in Table 23-9.
Figure 23-8 shows BDM serial port AC timing for the values in Table 23-9.
PSTCLK
DSCLK
D3
DSI
DSO
23-12
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 23-9. Debug AC Timing Specification
Characteristic
PST[3:0], DDATA[3:0] to PSTCLK valid
PSTCLK to PST[3:0], DDATA[3:0] hold
DSI-to-DSCLK setup
DSCLK-to-DSO hold
DSCLK cycle time
PSTCLK
PST[3:0], DDATA[3:0]
Figure 23-7. Real-Time Trace AC Timing
Current
Past
Figure 23-8. BDM Serial Port AC Timing
MCF5272 User's Manual
0-66 MHz
Min Max
— 8.5
1 —
1 —
4 —
5 —
D1
D2
D5
D4
Units
nS
nS
PSTCLKs
PSTCLKs
PSTCLKs
Next
Current