Motorola DigitalDNA ColdFire MCF5272 User Manual page 519

Table 23-20. GCI Master Mode Timing, PLIC PORTs 1, 2, 3
Name
P57 Delay from rising edge of GDCL1_OUT to Low-Z and valid data on
DOUT[1,3]
P58 Delay from rising edge of GDCL1_OUT to data valid on DOUT[1,3]
P59 Delay from rising edge of GDCL1_OUT to High-Z on DOUT[1,3]
P60 Data valid on DIN[1:2] before rising edge of GDCL1_OUT (setup
time)
P61 Data valid on DIN[1:2] after rising edge of GDCL1_OUT (hold time)
1
For most telecommunications applications the period of DFSC[1:3] should be set to 125 µS. Refer to clock
generator planning in PLIC chapter.
2
GDCL1_OUT must be less than 1/20th of the CPU operating frequency to ensure minimum jitter to CODECs
connected to Ports 1, 2, 3.
3
Same as DCL0 and FSC0 if internal clock generator configured for pass-through mode.
4
Based on generated GDCL1_OUT less than 1/20 of CPU clock frequency.
Figure 23-20 shows GCI master timings listed in Table 23-20.
GDCL1_OUT
P50
DFSC1
DFSC2
DFSC3
P57
DOUT1
DOUT3
P60
DIN1
DIN3
23.4.6 General-Purpose I/O Port AC Timing Specifications
Table 23-21 lists GPIO port timings.
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Characteristic
P51
P61
Figure 23-20. GCI Master Mode Timing
Chapter 23. Electrical Characteristics
Debug AC Timing Specifications
Min Max
— —
— —
— —
25 —
25 —
P58
Unit Name
30 nS
30 nS
30 nS
— nS
— nS
P52
P54
P53
P59
23-25