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7
Field
Reset
R/W
Address
Figure 16-10. UART Auxiliary Control Registers (UACRn)
Table 16-8 describes UACRn fields.
Bits
Name
7–3
—
Reserved, should be cleared.
2–1
RTSL
RTS level. Determines when RTS is negated by the receiver relative to the fullness of the receiver
FIFO. Note that RTS must first be manually asserted by a write to UOP0n.
00 FIFO level control disabled
01 Receiver FIFO ≥ 25% full
10 Receiver FIFO ≥ 50% full
11 Receiver FIFO ≥ 75% full
Receiver overrun can be prevented by using the RTS output to control the CTS input of the
transmitting device. Attempting to program a receiver and transmitter in the same channel for RTS
control is not permitted and disables RTS control for both.
0
IEC
Input enable control.
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external
transition on the CTS input (if UIMRn[COS] = 1).
16.3.10 UART Interrupt Status/Mask Registers
(UISRn/UIMRn)
The UART interrupt status registers (UISRn), Figure 16-11, provide status for all potential
interrupt sources. UISRn contents are masked by UIMRn. If corresponding UISRn and
UIMRn bits are set, the internal interrupt output is asserted. If a UIMRn bit is cleared, the
state of the corresponding UISRn bit has no effect on the output.
True status is provided in the UISRn regardless of UIMRn
settings. UISRn is cleared when the UART module is reset.
7
Field
COS
Reset
R/W
Address
MBAR + 0x114 (UISR0), 0x154 (UISR1); MBAR + 0x114 (UIMR0), 0x154 (UIMR1)
Figure 16-11. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
—
MBAR + 0x110 (UACR0), 0x150 (UACR1)
Table 16-8. UACRn Field Descriptions
6
ABC
RXFIFO
TXFIFO
Read only for status, write only for mask.
Chapter 16. UART Modules
3
0000_0000
Write only
Description
NOTE:
3
RXFTO
0000_0000
Register Descriptions
2
1
RTSL
2
1
DB
FFULL/RxRDY
0
IEC
0
TxRDY
16-13
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