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Table A-4. Interrupt Control Register Memory Map
MBAR
[31:24]
Offset
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003F
MBAR
[31:24]
Offset
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
0x0060
0x0064
0x0068
0x006C
0x0070
0x0074
0x0078
0x007C
MBAR
[31:24]
Offset
0x0080
0x0084
Port A Data Direction Register (PADDR)
0x0086
[23:16]
Interrupt Control Register 1 (ICR1)
Interrupt Control Register 2 (ICR2)
Interrupt Control Register 3 (ICR3)
Interrupt Control Register 4 (ICR4)
Interrupt Source Register (ISR)
Programmable Interrupt Transition Register (PITR)
Programmable Interrupt Wakeup Register (PIWR)
Reserved
Table A-5. Chip Select Register Memory Map
[23:16]
CS Base Register 0 (CSBR0)
CS Option Register 0 (CSOR0)
CS Base Register 1 (CSBR1)
CS Option Register 1 (CSOR1)
CS Base Register 2 (CSBR2)
CS Option Register 2 (CSOR2)
CS Base Register 3 (CSBR3)
CS Option Register 3 (CSOR3)
CS Base Register 4 (CSBR4)
CS Option Register 4 (CSOR4)
CS Base Register 5 (CSBR5)
CS Option Register 5 (CSOR5)
CS Base Register 6 (CSBR6)
CS Option Register 6 (CSOR6)
CS Base Register 7 (CSBR7)
CS Option Register 7 (CSOR7)
Table A-6. GPIO Port Register Memory Map
[23:16]
Port A Control Register (PACNT)
Appendix A. List of Memory Maps
List of Memory Map Tables
[15:8]
Programmable Interrupt
Vector Register (PIVR)
[15:8]
[15:8]
Reserved
Port A Data Register (PADAT)
[7:0]
[7:0]
[7:0]
A-3
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