Motorola DigitalDNA ColdFire MCF5272 User Manual page 518

Debug AC Timing Specifications
Table 23-19. GCI Slave Mode Timing, PLIC Ports 0–3 (Continued)
Name
P41 Data valid on DIN0 before rising edge of DCL0,
Data valid on DIN1 or DIN3 before rising edge of DCL1
P42 Data valid on DIN0 after rising edge of DCL0,
Data valid on DIN1 or DIN3 after rising edge of DCL1
Figure 23-19 shows GCI slave timings listed in Table 23-19.
DCL[0:1]
P30
P32
FSC[0,1]
DFSC[2,3]
P38
DOUT[0,1,3]
P41
DIN[0,1,3]
Table 23-20 lists timings for GCI master mode.
Table 23-20. GCI Master Mode Timing, PLIC PORTs 1, 2, 3
Name
1
P50 Delay from rising edge of GDCL1_OUT to rising edge of DFSC[1:3]
1
P51 Delay from rising edge of GDCL1_OUT to falling edge of DFSC[1:3]
2,3
P52 GDCL1_OUT clock period
2,4
P53 GDCL1_OUT pulse width low
2,4
P54 GDCL1_OUT pulse width high
23-24
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Characteristic
P31
P42
Figure 23-19. GCI Slave Mode Timing
Characteristic
MCF5272 User's Manual
Min
25
25
P34
P39
Min Max
— —
— —
20T —
45 50
45 50
Max Unit
— nS
— nS
P33
P35
P40
Unit Name
20 nS
20 nS
— nS
55 % of period
55 % of period