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16.5.2.2 Receiver
The receiver is enabled through its UCRn, as described in Section 16.3.5, "UART
Command Registers (UCRn)." Figure 16-26 shows receiver functional timing.
RxD
C1
Receiver
Enabled
USRn[RxRDY]
USRn[FFULL]
internal
module
select
Overrun
USRn[OE]
Manually asserted first time,
4
RTS
automatically negated if overrun occurs
UOP0[RTS] = 1
When the receiver detects a high-to-low (mark-to-space) transition of the start bit on RxD,
the state of RxD is sampled each 16× clock for eight clocks, starting one-half clock after
the transition (asynchronous operation) or at the next rising edge of the bit time clock
(synchronous operation). If RxD is sampled high, the start bit is invalid and the search for
the valid start bit begins again.
If RxD is still low, a valid start bit is assumed and the receiver continues sampling the input
at one-bit time intervals, at the theoretical center of the bit, until the proper number of data
bits and parity, if any, is assembled and one stop bit is detected. Data on the RxD input is
sampled on the rising edge of the programmed clock source. The lsb is received first. The
data is then transferred to a receiver holding register and USRn[RxRDY] is set. If the
character is less than eight bits, the most significant unused bits in the receiver holding
register are cleared.
After the stop bit is detected, the receiver immediately looks for the next start bit. However,
if a non-zero character is received without a stop bit (framing error) and RxD remains low
for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new
start bit were detected. Parity error, framing error, overrun error, and received break
conditions set the respective PE, FE, OE, RB error, and break flags in the USRn at the
received character boundary and are valid only if USRn[RxRDY] is set.
C2
C3
Status
Data
(C1)
Figure 16-26. Receiver Timing
Chapter 16. UART Modules
C25
C26
C27
Status
Data
C26
(C2)
is lost
Operation
C29
C28
C26, C27, and C82 are lost
Status
Status
Data
Data
(C3)
(C4)
Reset by
command
Automatically asserted
when ready to receive
16-25
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