Motorola DigitalDNA ColdFire MCF5272 User Manual page 47

Table ii Notational Conventions (Continued)
Instruction
dc Data cache
ic Instruction cache
# <vector> Identifies the 4-bit vector number for trap instructions
<> identifies an indirect data address referencing memory
<xxx> identifies an absolute address referencing memory
dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
+ Arithmetic addition or postincrement indicator
– Arithmetic subtraction or predecrement indicator
x Arithmetic multiplication
/ Arithmetic division
~ Invert; operand is logically complemented
& Logical AND
| Logical OR
^ Logical exclusive OR
<< Shift left (example: D0 << 3 is shift D0 left 3 bits)
>> Shift right (example: D0 >> 3 is shift D0 right 3 bits)
→ Source operand is moved to destination operand
←→ Two operands are exchanged
sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion
If <condition> Test the condition. If true, the operations after 'then' are performed. If the condition is false and the
then optional 'else' clause is present, the operations after 'else' are performed. If the condition is false
<operations> and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description
else as an example.
<operations>
Operand Syntax
Operations
About This Book
Terminology Conventions
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