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of an activated page. Each bank can have one open page. A device with two banks can have
two open pages. A device with four banks can have four open pages.
The lower addresses of the row address are compared against the page address register
content. If it does not match, the SDRAM controller precharges the open page on the
accessed bank and activates the new required page. After this, the SDRAM controller
executes the
or
READ
is updated. This is called a page miss.
After a bank is activated, it remains activated until the next page access causing a page miss.
A precharge of a deactivated bank is allowed and simply ignored by the SDRAM.
If a memory access is to an open page only the
SDRAM. This is called a page hit.
In two-page SDRAMs, banks 2 and 3 are invalid and must not be addressed. To avoid
address aliasing, the user should restrict the chip select address range to the space available
in the SDRAMs.
9.5 SDRAM Registers
The SDRAM configuration register (SDCR) and the SDRAM timing register (SDTR) are
described in the following sections. Note that SDRAM provides a mode register that is not
part of the SDRAM controller memory model. The SDRAM mode register is automatically
configured during initialization.
9.5.1 SDRAM Configuration Register (SDCR)
SDCR is used to configure the SDRAM controller address multiplexers for the type of
SDRAM devices used on the system board.
15
14
13
Write
—
MCAS
Reset
0
00
R/W
Addr
Figure 9-3. SDRAM Configuration Register (SDCR)
Table 9-7 describes SDCR fields.
command. Concurrently, the page address register of the bank
WRITE
12
11
10
—
BALOC
00
001
Read/Write
Chapter 9. SDRAM Controller
or
READ
WRITE
8
7
6
5
GSL
—
0
00
MBAR + 0x0180
SDRAM Registers
command is issued to the
4
3
2
1
REG
INV SLEEP ACT
0
1
0
0
Read-only
0
INIT
0
R/W
9-7
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