Bus Errors - Motorola DigitalDNA ColdFire MCF5272 User Manual

Bus Errors

dedicated to an external peripheral. It is possible to have multiple external peripherals share
an INTx pin but software must then determine which peripheral caused the interrupt. The
interrupt priority level and the signal level of each interrupt pin are individually
programmable.
The MCF5272 continuously samples the external interrupt input signals and synchronizes
and debounces these signals. An interrupt request must be held constant for at least two
consecutive CLK periods to be considered a valid input. MCF5272 latches the interrupt and
the interrupt controller responds as programmed. The interrupt service routine must clear
the latch in the ICR registers.
All internal interrupts are level sensitive only. External
interrupts are edge-sensitive as programmed in the PITR.
Interrupts must remain stable and held valid for two clock
cycles while they are internally synchronized and latched.
The MCF5272 takes an interrupt exception for a pending interrupt within one instruction
boundary after processing any other pending exception with a higher priority. Thus, the
MCF5272 executes at least one instruction in an interrupt exception handler before
recognizing another interrupt request.
20.10 Bus Errors
The system hardware can use the transfer error acknowledge (TEA) signal to abort the
current bus cycle when a fault is detected. A bus error is recognized during a bus cycle when
TEA is asserted.
The signal TEA is not intended for use in normal operation
since each chip select can be programmed to automatically
terminate a bus cycle at a time defined by the bits programmed
into the wait state field of the Chip Select Option Register.
There is an on chip bus monitor which can be configured to
generate an internal TEA signal.
When the MCF5272 recognizes a bus error condition for an access, the access is terminated
immediately. An access that requires more than one transfer aborts without completing the
remaining transfers if TEA is asserted, regardless of whether the access uses burst or
non-burst transfers.
Figure 20-20 shows a longword write access to a 32-bit port with a transfer error.
20-22
NOTE:
NOTE:
MCF5272 User's Manual