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Paragraph
Number
12.4.2
USB Configuration and Interface Changes ................................................ 12-30
12.4.3
FIFO Configuration .................................................................................... 12-30
12.4.4
Data Flow.................................................................................................... 12-31
12.4.4.1
Control, Bulk, and Interrupt Endpoints .................................................. 12-32
12.4.4.1.1
12.4.4.1.2
12.4.4.2
Isochronous Endpoints............................................................................ 12-33
12.4.4.2.1
12.4.4.2.2
12.4.5
Class- and Vendor-Specific Request Operation ......................................... 12-34
12.4.6
remote wakeup and resume Operation........................................................ 12-34
12.4.7
Endpoint Halt Feature................................................................................. 12-35
12.5
Line Interface .................................................................................................. 12-35
12.5.1
Attachment Detection ................................................................................. 12-35
12.5.2
PCB Layout Recommendations.................................................................. 12-36
13.1
Introduction....................................................................................................... 13-1
13.2
GCI/IDL Block ................................................................................................. 13-3
13.2.1
GCI/IDL B- and D-Channel Receive Data Registers ................................... 13-4
13.2.2
GCI/IDL B- and D-Channel Transmit Data Registers.................................. 13-5
13.2.3
GCI/IDL B- and D-Channel Bit Alignment ................................................. 13-6
13.2.3.1
B-Channel Unencoded Data ..................................................................... 13-6
13.2.3.2
B-Channel HDLC Encoded Data.............................................................. 13-7
13.2.3.3
D-Channel HDLC Encoded Data ............................................................. 13-7
13.2.3.4
D-Channel Unencoded Data ..................................................................... 13-8
13.2.3.5
GCI/IDL D-Channel Contention ............................................................. 13-9
13.2.4
GCI/IDL Looping Modes ............................................................................. 13-9
13.2.4.1
Automatic Echo Mode ............................................................................ 13-10
13.2.4.2
Local Loopback Mode ............................................................................ 13-10
13.2.4.3
Remote Loopback Mode......................................................................... 13-10
13.2.5
GCI/IDL Interrupts ..................................................................................... 13-11
13.2.5.1
GCI/IDL Periodic Frame Interrupt ......................................................... 13-11
13.2.5.2
GCI Aperiodic Status Interrupt.............................................................. 13-11
13.2.5.3
Interrupt Control ..................................................................................... 13-12
13.3
PLIC Timing Generator .................................................................................. 13-12
13.3.1
Clock Synthesis........................................................................................... 13-12
13.3.2
Super Frame Sync Generation .................................................................... 13-13
13.3.3
Frame Sync Synthesis................................................................................. 13-14
13.4
PLIC Register Memory Map .......................................................................... 13-15
CONTENTS
IN Endpoints....................................................................................... 12-32
OUT Endpoints................................................................................... 12-32
IN Endpoints....................................................................................... 12-33
OUT Endpoints................................................................................... 12-33
Chapter 13
Physical Layer Interface Controller (PLIC)
Title
Contents
Page
Number
xiii
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