Processor Bus Output Timing Specifications - Motorola DigitalDNA ColdFire MCF5272 User Manual

AC Electrical Specifications
Table 23-8. Processor Bus Output Timing Specifications
Name
B6a SDCLK to chip selects (CS[6:0]) valid
B6b SDCLK to byte enables (BS[3:0]) valid
B6c SDCLK to output enable (OE) valid
B6d SDCLK to write enable (R/W) valid
B6e SDCLK to reset output (RSTO) valid
B7a SDCLK to control output (CS[6:0], OE) invalid (output hold)
B7b SDCLK to control output (BS[3:0], R/W) invalid (output hold)
B7c SDCLK to reset output (RSTO) invalid (output hold)
B8 SDCLK to address (A[22:0]) valid
B9 SDCLK to address (A[22:0]) invalid (output hold)
B11 SDCLK to data output (D[31:0]) valid
2
B12 SDCLK to data output (D[31:0]) invalid (output hold)
B13 SDCLK to data output (D[31:0]) high impedance
1
All timing references to SDCLK are given to its rising edge when bit 3 of the SDRAM control register is 0.
2
Data output is held valid for one CPU clock period after deassertion of BS[3:0]
Above 48 MHz, the memory bus may need to be configured for
one wait state. It is the responsibility of the user to determine
the actual frequency at which to insert a wait state since this
depends on the access time of SRAM or SDRAM used in a
particular system implementation.
Wait states are inserted for SRAM accesses by programming
bits 6–2 of the chip select option registers.
A wait state is added for SDRAM read accesses by setting bit
4 of the SDRAM control register.
Read/write SRAM bus timings listed in Table 23-8 are shown in Figure 23-3, Figure 23-4,
Figure 23-5, and Figure 23-6.
23-8
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1
Characteristic
Control Outputs
Address and Attribute Outputs
Data Outputs
NOTE:
MCF5272 User's Manual
0–66 MHz
Unit
Min Max
— 11 nS
— 8.5 nS
— 8.5 nS
— 8 nS
— 7.4 nS
2 — nS
1.5 — nS
4 — nS
— 8.5 nS
2.5 — nS
— 11 nS
1 — nS
— 6 nS