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6. Interface #1 Descriptor
7. Endpoint #3 Descriptor
8. Configuration #2 Descriptor
9. Interface #0 Descriptor
10. Endpoint #1 Descriptor
11. Configuration #3 Descriptor
12. Interface #0 Descriptor
13. Endpoint #1 Descriptor
14. Endpoint #2 Descriptor
12.3.4 USB Module Access Times
The access times for the USB module depend on whether the access is to a register, to an
endpoint FIFO (EPnDAT register), or to the configuration RAM.
12.3.4.1 Registers
The USB module registers are accessed through the internal S-bus. Each register access
takes 3 clock cycles for reads and writes.
12.3.4.2 Endpoint FIFOs
The FIFO access time depends on the size, the time between accesses, and whether the
previous FIFO access was for the same endpoint. After a longword access to an endpoint's
FIFO, the next longword in the FIFO is cached for a quicker access time on the next
longword read. This mechanism is reset every time another endpoint is accessed.
Table 12-19 shows the access times for the FIFOs.
Access Type
Byte
Word
Long (back to back)
Long (1 clock gap)
Long (2 clock gap)
Long (3+ clock gap)
12.3.4.3 Configuration RAM
The configuration RAM is longword accessible only. Access times for reads from the
configuration RAM are eight clock cycles per access. Clock cycle access times for
back-to-back writes to the configuration RAM are 3-5-5-5-5-5... Access times for writes
separated by at least 1 clock cycle are 3-3-3-3-3-3...
Table 12-19. USB FIFO Access Timing
Read
5
6
8-4-6-6-6-6...
8-3-5-5-5-5...
8-3-4-4-4-4...
8-3-3-3-3-3...
Chapter 12. Universal Serial Bus (USB)
Register Description and Programming Model
Write
4
4
4-6-6-6-6-6...
4-5-5-5-5-5...
4-4-4-4-4-4...
4-4-4-4-4-4...
12-29
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