Motorola DigitalDNA ColdFire MCF5272 User Manual page 202

Performance
Table 9-10. SDRAM Controller Performance, 32–Bit Port, (RCD = 0, RP = 0) (Contin-
SDRAM Access
Single-beat write
Burst read
Burst write
In Table 9-11, the timing configuration is RTP = 61, RC = negligible, RCD = 1, RP = 1, and
CLT = 1.
Table 9-11. SDRAM Controller Performance (RCD = 1, RP = 1), 16-Bit Port
Single-beat read
Single-beat
longword read
Single-beat write
Single-beat
longword write
Burst read
Burst write
In Table 9-12, the timing configuration is RTP = 61, RC = negligible, RCD = 0 (or 1),
RP = 1 (or 0), and CLT = 1.
Table 9-12. SDRAM Controller Performance, 16-Bit Port, (RCD=0, RP=1)
Single-beat read
9-12
Page miss
Page hit
Page miss
Page hit
Page miss
Page hit
SDRAM Access
Page miss
Page hit
Page miss
Page hit
Page miss
Page hit
Page miss
Page hit
Page miss
Page hit
Page miss
Page hit
or (RCD=1, RP = 0)
SDRAM Access
Page miss 8
Page hit
MCF5272 User's Manual
Number of System Clock Cycles
REG = 0, INV = 0
5
3
7-1-1-1 = 10
5-1-1-1 = 8
5-1-1-1 = 8
3-1-1-1 = 6
Number of System Clock Cycles
REG = 0, INV = 0 REG = 1, INV = 0
9 10
5 6
9-1 10-1
5-1 6-1
7 7
3 3
7-1 7-1
3-1 3-1
9-1-1-1-1-1-1-1 = 16 10-1-1-1-1-1-1-1 = 17
5-1-1-1-1-1-1-1 = 12 6-1-1-1-1-1-1-1 = 13
7-1-1-1-1-1-1-1 = 14 7-1-1-1-1-1-1-1 = 14
3-1-1-1-1-1-1-1 = 10 3-1-1-1-1-1-1-1 = 10
Number of System Clock Cycles
REG = 0, INV = 0
9
5 6
REG = 0, INV = 0
5
3
8-1-1-1 = 11
6-1-1-1 = 9
5-1-1-1 = 8
3-1-1-1 = 6
REG = 1, INV = 0