Table of Contents
Advertisement
Differences between MCF5272 FEC and MPC860T FEC
Table 11-35. TxBD Field Descriptions (Continued)
Bits
Name
-
Data Length
-
Tx Buffer Pointer Written by the user. The transmit buffer pointer, which contains the address of the
An underrun occurs when, during transmit, the transmit FIFO empties before the end of the
frame. Then, a bad CRC is appended to the partially transmitted data. In addition, the UN
bit is set in the last BD for the current frame. This situation can occur if the FEC cannot
access an internal bus, or if the next BD in the frame is not available.
Anytime the software driver sets an R bit in a transmit
descriptor,
X_DES_ACTIVE.
11.7 Differences between MCF5272 FEC and
MPC860T FEC
The MCF5272 features the same FEC as the MPC860T with a few differences. The
following list pertains to the MCF5272.
• Limited throughput full-duplex 100 Mbps operation. External bus use is the limiting
factor.
• Only big-endian mode is supported for buffer descriptors and buffers.
• Separate interrupt vectors for Rx, Tx and non-time critical interrupts
• Interrupt priority is set in the interrupt controller
• The formula for calculating E_MDC clock frequency differs between MCF5272 and
MPC860T:
— MCF5272: E_MDC_FREQUENCY= system frequency / (4 * MII_SPEED)
— MPC860T: E_MDC_FREQUENCY= system frequency / (2 * MII_SPEED)
MCF5272 ethernet controller signal names are generally
identical to those used in the MPC860T, except for a prefix of
'E_'. For example, MDC in the MPC860T corresponds to
E_MDC in the MCF5272.
11-38
Written by the user. Data length is the number of octets the FEC should transmit
from this BD's data buffer. It is never modified by the FEC. Bits [10–0] are used
by the DMA engine; bits [15–11] are ignored.
associated data buffer, may be even or odd. The buffer must reside in memory
external to the FEC. This value is never modified by the FEC.
NOTE:
the
driver
should
NOTE:
MCF5272 User's Manual
Description
immediately
write
to
Advertisement
Table of Contents
