Aperiodic Status Register (Pasr) - Motorola DigitalDNA ColdFire MCF5272 User Manual

Bits Name
4 B2TDE B2 data transmit data empty. This bit is set when the data in the PLTB2 transmit data
register for the respective port has been transferred to the transmit shadow register. This
bit is cleared when the CPU writes data to PLTB2.
3 B1TDE B1 data transmit data empty. This bit is set when the data in the PLTB1 transmit data
register for the respective port has been transferred to the transmit shadow register. This
bit is cleared when the CPU writes data to PLTB1.
2 DRDF D receive data full. This bit indicates that the D receive data register for the respective port
is full. DRDF is cleared when the CPU reads the receive data register PLRD.
1 B2RDF B2 receive data full. This bit indicates that the B2 receive data register for the respective
port is full. B2RDF is cleared when the CPU reads the receive data register PLRB2.
0 B1RDF B1 receive data full. This bit indicates that the B1 receive data register for the respective
port is full. B1RDF is cleared when the CPU reads the receive data register PLRB1.

13.5.11 Aperiodic Status Register (PASR)

All bits in this register are read only and are set on hardware or software reset.
15 14 13
Field GCR GCT GMR
3 3 3
Reset
R/W
Addr
Figure 13-23. Aperiodic Status Register (PASR)
The PASR register is a 16-bit register containing the aperiodic interrupt status information
for the C/I and monitor channel transmit and receive registers for all four ports on the
MCF5272. An aperiodic interrupt condition remains asserted as long as any one of the bits
within the PASR register is set.
Bits Name
15, 11, 7, 3 GCRn
14, 10, 6, 2 GCTn
Table 13-5. P0PSR–P3PSR Field Descriptions
12 11 10 9
GMT GCR GCT GMR
3 2 2 2
0000_0000_0000_0000
Table 13-6. PASR Field Descriptions
GCI C/I received. When set, this bit indicates that valid new data has been written to
a GCI C/I receive register. An interrupt is queued when this bit is set if the GCR
interrupt enable bit has been set in the corresponding PLICR register. The GCR bit
and associated interrupt are automatically cleared when the corresponding PLGCIR
register has been read by the CPU.
GCI C/I transmitted. When set, this bit indicates that a C/I register is empty. An
interrupt is queued when this bit is set if the GCT interrupt enable bit has been set in
the corresponding PLICR register. The GCT bit and associated interrupt are
automatically cleared when the PGCITSR register has been read by the CPU.
Chapter 13. Physical Layer Interface Controller (PLIC)
Description
8 7 6 5
GMT GCR GCT GMR
2 1 1 1
Read Only
MBAR + 0x38C
Description
PLIC Registers
4 3 2 1
GMT GCR GCT GMR
1 0 0 0
0
GMT
0
13-25