Motorola DigitalDNA ColdFire MCF5272 User Manual page 28

Figure
Number
15-4 Timer Capture Registers (TCR0–TCR3) .................................................................... 15-5
15-5 Timer Counter (TCN0–TCN3) ................................................................................... 15-5
15-6 Timer Event Registers (TER0–TER3)........................................................................ 15-5
16-1 Simplified Block Diagram .......................................................................................... 16-1
16-2 UART Mode Registers 1 (UMR1n)............................................................................ 16-5
16-3 UART Mode Register 2 (UMR2n) ............................................................................. 16-6
16-4 UART Status Registers (USRn).................................................................................. 16-7
16-5 UART Clock-Select Registers (UCSRn) .................................................................... 16-9
16-6 UART Command Registers (UCRn) .......................................................................... 16-9
16-7 UART Receiver Buffer (URBn) ............................................................................... 16-11
16-8 UART Transmitter Buffers (UTBn) ......................................................................... 16-12
16-9 UART Input Port Change Registers (UIPCRn) ........................................................ 16-12
16-10 UART Auxiliary Control Registers (UACRn) ......................................................... 16-13
16-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 16-13
16-12 UART Divider Upper Registers (UDUn) ................................................................. 16-14
16-13 UART Divider Lower Registers (UDLn) ................................................................. 16-15
16-14 UART Autobaud Upper Registers (UABUn) ........................................................... 16-15
16-15 UART Autobaud Lower Registers (UABLn) ........................................................... 16-15
16-16 UART Transmitter FIFO Registers (UTFn) ............................................................. 16-16
16-17 UART Receiver FIFO Registers (URFn) ................................................................. 16-16
16-18 UART Fractional Precision Divider Control Registers (UFPDn) ............................ 16-17
16-19 UART Input Port Registers (UIPn)........................................................................... 16-18
16-20 UART Output Port Command Registers (UOP1/UOP0).......................................... 16-18
16-21 UART Block Diagram Showing External and Internal Interface Signals ................ 16-19
16-22 UART/RS-232 Interface ........................................................................................... 16-20
16-23 Clocking Source Diagram......................................................................................... 16-21
16-24 Transmitter and Receiver Functional Diagram......................................................... 16-23
16-25 Transmitter Timing ................................................................................................... 16-24
16-26 Receiver Timing........................................................................................................ 16-25
16-27 Automatic Echo ........................................................................................................ 16-28
16-28 Local Loop-Back ...................................................................................................... 16-28
16-29 Remote Loop-Back ................................................................................................... 16-29
16-30 Multidrop Mode Timing Diagram ............................................................................ 16-30
16-31 UART Mode Programming Flowchart ..................................................................... 16-32
17-1 Port A Control Register (PACNT).............................................................................. 17-3
17-2 Port B Control Register (PBCNT) .............................................................................. 17-5
17-3 Port D Control Register (PDCNT).............................................................................. 17-8
17-4 Port A Data Direction Register (PADDR)................................................................ 17-10
17-5 Port B Data Direction Register (PBDDR) ................................................................ 17-10
17-6 Port C Data Direction Register (PCDDR) ................................................................ 17-11
17-7 Port x Data Register (PADAT, PBDAT, and PCDAT) ............................................ 17-12
18-1 PWM Block Diagram (3 Identical Modules).............................................................. 18-1
18-2 PWM Control Registers (PWCRn)............................................................................. 18-3
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ILLUSTRATIONS
Title
MCF5272 User's Manual
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