Motorola DigitalDNA ColdFire MCF5272 User Manual page 210

SDRAM Interface
T0 T1
SDCLK
CF2 Core
Issue
Address
SDCLKE
SDADR[13:0]
A10_PRECHG
SDBA[1:0]
SDCS
RAS0
CAS0
SDWE
BS[3:0]
D[31:0]
Figure 9-11. SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1
In the burst-write, page-hit example, shown in Figure 9-12, after the SDRAM controller
determines that the access is a page hit in T2, the burst transfer begins in T3.
9-20
T2 T3 T4
Precharge
Page
Old Page
Hit or
Miss?
Bank x
MCF5272 User's Manual
T5 T6 T7
Write
Activate
1
New Page
Row Col
Row
Bank y
Data
T8 T9 T10
Write
3
Write Write
2 4
Col Col Col
Bank y
Data Data Data
T1