Dma Interrupt Register (Dir) - Motorola DigitalDNA ColdFire MCF5272 User Manual

DMA Controller Registers
Table 10-2. DMR Field Descriptions (Continued)
Bits Name
4–2 SRCT Source addressing type. Used internal to the MCF5272 to qualify the address bits. The value
should be compatible with the CSCRn[TM] value used for external RAM or peripheral device
access.
000 Reserved
001 User data access
010 User code access
011 Reserved
100 Reserved
101 Supervisor data access
110 Supervisor code access
111 Reserved
1–0 SRCS Source data transfer type. Determines the amount of data the DMA controller fetches and buffers
data from the source address. When there are enough bytes to perform a destination data write of
the size programmed in DSTS, the data is written to the destination address. Thus source
accesses can be longword type and destination addresses can be line burst type. In this case, 4
longword reads are performed followed by an indivisible burst write of 4 longwords.
The most efficient data transfer method is to use longword or line burst transfer types.

10.3.2 DMA Interrupt Register (DIR)

The DIR, Figure 10-2, contains status bits and their corresponding interrupt enables.
15 13
Field —
Reset
R/W
Addr
Table 10-3 describes DIR fields.
Bits Name
15–13 — Reserved, should be cleared.
12 INVEN Invalid combination interrupt enable.
0 INV interrupt is disabled.
1 INV interrupt is enabled.
10-4
SRCS Data Transfer Type
00 Longword
01 Byte
10 Word
11 16-byte line burst
12 11 10
INVEN ASCEN — TEEN TCEN
0000_0000_0000_0000
Figure 10-2. DMA Interrupt Register (DIR)
Table 10-3. DIR Field Descriptions
MCF5272 User's Manual
Description
Address Incremented by
4
1
2
16. Valid only for SDRAM.
9 8 7
—
R/W
MBAR + 0x00E6
Description
5 4 3 2
INV ASC — TE
1 0
TC